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! " white electronic designs 32 pin, rectangular ceramic leadless chip carrier (package 601) mil-std-883 compliant devices available commercial, industrial and military temperature range 5 volt power supply low power cmos 2v data retention devices available (low power version) ttl compatible inputs and outputs
access times 15, 17, 20, 25, 35, 45, 55ns revolutionary, center power/ground pinout jedec approved ? 32 lead ceramic soj (package 101) 36 lead ceramic flat pack (package 226) evolutionary, corner power/ground pinout jedec approved 32 pin ceramic dip (package 300) 32 lead ceramic soj (package 101) 32 lead ceramic flat pack (package 206)

a 0-16 address inputs i/o 0-7 data input/output cs chip select oe output enable we write enable v cc +5.0v power gnd ground

september 2002 rev. 5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 a0 a1 a2 a3 cs i/o1 i/o2 v cc gnd i/o3 i/o4 we a4 a5 a6 a7 a16 a15 a14 a13 oe i/o8 i/o7 gnd v cc i/o6 i/o5 a12 a11 a10 a9 a8 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 nc a16 a14 a12 a7 a6 a5 a4 a3 a2 a1 a0 i/o0 i/o1 i/o2 gnd v cc a15 nc we a13 a8 a9 a11 oe a10 cs i/o7 i/o6 i/o5 i/o4 i/o3 we a13 a8 a9 a11 oe a10 cs i/o7 a7 a6 a5 a4 a3 a2 a1 a0 i/o 0 5 6 7 8 9 10 11 12 13 29 28 27 26 25 24 23 22 21 i/o1 i/02 v ss i/o3 i/o4 i/o5 i/o6 a12 a14 a16 a18 v cc a15 a17 4 3 2 1 32 31 30 14 15 16 17 18 19 20 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 nc a0 a1 a2 a3 cs i/o0 i/o1 v cc gnd i/o2 i/o3 we a4 a5 a6 a7 nc nc a16 a15 a14 a13 oe i/o7 i/o6 gnd v cc i/o5 i/o4 a12 a11 a10 a9 a8 nc

#$%& white electronic designs input leakage current i li v cc = 5.5, v in = gnd to v cc 10 10 10 a output leakage current i lo cs = v ih , oe = v ih , v out = gnd to v cc 10 10 10 a operating supply current i cc cs = v il , oe = v ih , f = 5mhz, vcc = 5.5 150 150 150 ma standby current i sb cs = v ih , oe = v ih , f = 5mhz, vcc = 5.5 15 15 15 ma output low voltage v ol i ol = 2.1ma, vcc = 4.5 0.4 0.4 0.4 v output high voltage v oh i oh = -1.0ma, vcc = 4.5 2.4 2.4 2.4 v ! !" #$ # input leakage current i li v cc = 5.5, v in = gnd to v cc 10 10 10 10 a output leakage current i lo cs = v ih , oe = v ih , v out = gnd to v cc 10 10 10 10 a operating supply current i cc cs = v il , oe = v ih , f = 5mhz, vcc = 5.5 150 150 150 150 ma standby current i sb cs = v ih , oe = v ih , f = 5mhz, vcc = 5.5 20 20 20 15 ma output low voltage v ol i ol = 8ma, vcc = 4.5 0.4 0.4 0.4 0.4 v output high voltage v oh i oh = -4.0ma, vcc = 4.5 2.4 2.4 2.4 2.4 v % & ' ( % ))
' ) * +, operating temperature t a -55 +125 c storage temperature t stg -65 +150 c signal voltage relative to gnd v g -0.5 vcc+0.5 v junction temperature t j 150 c supply voltage v cc -0.5 7.0 v +, supply voltage v cc 4.5 5.5 v input high voltage v ih 2.2 v cc + 0.3 v input low voltage v il -0.5 +0.8 v operating temp. (mil.) ta -55 +125 c ( )*- * . h x x standby high z standby l l h read data out active l x l write data in active l h h out disable high z active this parameter is guaranteed by design but not tested. /01 2*34 input capacitance c in v in = 0v, f = 1.0mhz 32 pin csoj, dip, 15 to 55 20 pf flat pack evolutionary 36 pin flat pack and 15 to 25 12 pf 32 pin csoj revolutionary 35 to 55 20 pf output capacitance c out v out = 0v, f = 1.0mhz 32 pin csoj, dip, 15 to55 20 pf flat pack evolutionary 36 pin flat pack and 15 to 25 12 pf 32 pin csoj revolutionary 35 to 55 20 pf 32 pin clcc 15 to 55 15 pf note: dc test conditions: v ih = v cc -0.3v, v il = 0.3v

! " white electronic designs +, ! !" #$ # * /, write cycle time t wc 15 17 20 25 35 45 55 ns chip select to end of write t cw 14 14 15 20 25 30 45 ns address valid to end of write t aw 14 15 15 20 25 30 45 ns data valid to end of write t dw 10 10 12 15 20 25 25 ns write pulse width t wp 14 14 15 20 25 30 45 ns address setup time t as 00 00 0 0 0 ns address hold time t ah 00 00 0 0 0 ns output active from end of write t ow 1 33 33 4 4 4 ns write enable to output in high z t whz 1 10 10 12 15 20 25 25 ns data hold time t dh 00 00 0 0 0 ns +, ! !" #$ # * /, read cycle time t rc 15 17 20 25 35 45 55 ns address access time t aa 15 17 20 25 35 45 55 ns output hold from address change t oh 0000000 ns chip select access time t acs 15 17 20 25 35 45 55 ns output enable to output valid t oe 10 10 12 15 20 25 30 ns chip select to output in low z t clz 1 3333333 ns output enable to output in low z t olz 1 0000000 ns chip disable to output in high z t chz 1 10 10 10 12 20 20 20 ns output disable to output in high z t ohz 1 10 10 10 12 20 20 20 ns notes: vz is programmable from -2v to +7v. i ol & i oh programmable from 0 to 16ma. tester impedance z 0 = 75 v z is typically the midpoint of v oh and v ol . i ol & i oh are adjusted to simulate a typical resistive load circuit. ate tester includes jig capacitance. ) 2 input pulse levels v il = 0, v ih = 3.0 v input rise and fall 5 ns input and output reference level 1.5 v output timing reference level 1.5 v (
( 1. this parameter is guaranteed by design but not tested. 1. this parameter is guaranteed by design but not tested.

#$%& white electronic designs ws32k32-xhx ' 5 )

)
) a ddress data i/o read cycle 1 (cs = oe = v il , we = v ih ) t aa t oh t rc data valid previous data valid read cycle 2 (we = v ih ) t aa t rc a ddress cs oe data i/o t acs t chz t clz t oe t olz t ohz high impedance data valid a ddress data i/o write cycle 1, we controlled t aw t cw t ah t wp t dw t whz t as t ow t dh t wc data valid cs we a ddress data i/o write cycle 2, cs controlled t aw t as t cw t ah t wp t dh t dw t wc cs we data valid

! " white electronic designs all linear dimensions are millimeters and parenthetically in inches 6' )
! 1.27 (0.050) typ 21.1 (0.830) 0.25 (0.010) 19.1 (0.750) typ 11.23 (0.442) 0.30 (0.012) 3.96 (0.156) max 0.2 (0.008) 0.05 (0.002) 9.55 (0.376) 0.25 (0.010) 1.27 (0.050) 0.25 (0.010) 0.89 (0.035) radius typ

#$%& white electronic designs 6' " ) # 6 all linear dimensions are millimeters and parenthetically in inches 10.41 (0.410) 0.13 (0.005) 3.18 (0.125) max 0.127 (0.005) + 0.05 (0.002) ? 0.025 (0.001) 1.27 (0.050) typ 7.87 (0.310) 0.13 (0.005) 19.05 (0.750) typ 6.35 (0.250) min 0.43 (0.017) 0.05 (0.002) 20.83 (0.820) 0.25 (0.010) 6' " " ) # 6 all linear dimensions are millimeters and parenthetically in inches 23.37 (0.920) 0.25 (0.010) 32.64 (1.285) typ 12.95 (0.510) 0.13 (0.005) 3.8 (0.150) typ 2.72 (0.107) max 0.127 (0.005) 0.05 (0.002) pin 1 identifier 1.27 (0.050) typ 21.59 (0.850) typ 38.1 (1.50) 0.4 (0.015) 12.7 (0.500) 0.5 (0.020) 5.1 (0.200) 0.25 (0.010) 0.43 (0.017) 0.05 (0.002)

! " white electronic designs 6' '
) $ 7) all linear dimensions are millimeters and parenthetically in inches 2.5 (0.100) typ 1.27 (0.050) 0.1 (0.005) 0.46 (0.018) 0.05 (0.002) 0.99 (0.039) 0.51 (0.020) 3.2 (0.125) min 0.25 (0.010) 0.05 (0.002) 15.25 (0.600) 0.25 (0.010) 42.8 (1.686) max 5.13 (0.202) max

#$%& white electronic designs 7.62 (0.300) typ 5.08 (0.200) typ 3.81 (0.150) typ 10.16 (0.400) typ 0.38 (0.015) x 45 pin 1 identifier 0.56 (0.022) 0.71 (0.028) 11.25 (0.443) 14.15 (0.457) 13.79 (0.543) 14.15 (0.557) 1.63 (0.064) 2.54 (0.100) pin 1 1.02 (0.040) x 45 3 places 6' " ' ) ( all linear dimensions are millimeters and parenthetically in inches

! " white electronic designs )*5(8 blank = gold plated leads a = solder dip leads ) *' )8 m = military screened -55c to +125c i = industrial -40c to +85c c = commercial 0c to +70c 6'8 c = 32 pin ceramic .600" dip (package 300) cl = 32 pin rectangular ceramic leadless chip carrier (package 601) de = 32 lead ceramic soj (package 101) evolutionary dr = 32 lead ceramic soj (package 101) revolutionary f = 36 lead ceramic flat pack (package 226) fe = 32 lead ceramic flat pack (package 220) **34 * 6 l = low power for 2v data retention '79*!#:6* *: ( (* *)'* ; +, 2 data retention supply voltage v dr cs v cc -0.2v 2.0 5.5 v data retention current i ccdr2 v cc = 2v 2 ma (

) ' % 5

#$%& white electronic designs
) 6' 128k x 8 sram monolithic 55ns 32 lead soj revol (dr) 5962-96691 05hux 128k x 8 sram monolithic 45ns 32 lead soj revol (dr) 5962-96691 06hux 128k x 8 sram monolithic 35ns 32 lead soj revol (dr) 5962-96691 07hux 128k x 8 sram monolithic 25ns 32 lead soj revol (dr) 5962-96691 08hux 128k x 8 sram monolithic 20ns 32 lead soj revol (dr) 5962-96691 09hux 128k x 8 sram monolithic 17ns 32 lead soj revol (dr) 5962-96691 10hux 128k x 8 sram monolithic 15ns 32 lead soj revol (dr) 5962-96691 11hux 128k x 8 sram monolithic 55ns 32 lead soj evol (de) 5962-96691 05htx 128k x 8 sram monolithic 45ns 32 lead soj evol (de) 5962-96691 06htx 128k x 8 sram monolithic 35ns 32 lead soj evol (de) 5962-96691 07htx 128k x 8 sram monolithic 25ns 32 lead soj evol (de) 5962-96691 08htx 128k x 8 sram monolithic 20ns 32 lead soj evol (de) 5962-96691 09htx 128k x 8 sram monolithic 17ns 32 lead soj evol (de) 5962-96691 10htx 128k x 8 sram monolithic 15ns 32 lead soj evol (de) 5962-96691 11htx 128k x 8 sram monolithic 55ns 32 pin dip (c) 5962-96691 05hyx 128k x 8 sram monolithic 45ns 32 pin dip (c) 5962-96691 06hyx 128k x 8 sram monolithic 35ns 32 pin dip (c) 5962-96691 07hyx 128k x 8 sram monolithic 25ns 32 pin dip (c) 5962-96691 08hyx 128k x 8 sram monolithic 20ns 32 pin dip (c) 5962-96691 09hyx 128k x 8 sram monolithic 17ns 32 pin dip (c) 5962-96691 10hyx 128k x 8 sram monolithic 15ns 32 pin dip (c) 5962-96691 11hyx 128k x 8 sram monolithic 55ns 36 pin flatpack (f) 5962-96691 05hxx 128k x 8 sram monolithic 45ns 36 pin flatpack (f) 5962-96691 06hxx 128k x 8 sram monolithic 35ns 36 pin flatpack (f) 5962-96691 07hxx 128k x 8 sram monolithic 25ns 36 pin flatpack (f) 5962-96691 08hxx 128k x 8 sram monolithic 20ns 36 pin flatpack (f) 5962-96691 09hxx 128k x 8 sram monolithic 17ns 36 pin flatpack (f) 5962-96691 10hxx 128k x 8 sram monolithic 15ns 36 pin flatpack (f) 5962-96691 11hxx

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